I'm thrilled to share that our research paper, "DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks," has been accepted for presentation at the International Symposium on Quality Electronic Design (ISQED) 2024.
In our work, we present a novel methodology that markedly diminishes structural signatures in logic-locked circuits that are typically exploited by machine learning-based attacks. This universally applicable approach significantly lowers the accuracy of these attacks to near random-guessing levels, enhancing the security of logic locking techniques.
A special shoutout to my amazing co-authors - my Ph.D. advisor Prof. Pierluigi Nuzzo, and my peers Kaixin Yang and Subhajit Dutta Chowdhury - at USC.
#ISQED2024 #LogicLocking #MachineLearning #HardwareSecurity #IPprotection #USC
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As hardware becomes more ubiquitous in our daily lives, protecting intellectual property (IP) and ensuring secure operations are paramount concerns. I'm thrilled to announce that our research on hardware security has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems! Our work focuses on the security of Sequential Logic Locking, a class of IP protection methods. In our paper, we present Fun-SAT, a functional corruptibility-guided SAT-based attack that can efficiently estimate the minimum unrolling depth required for a successful SAT attack to prune out of the search space all the wrong keys. This is a major improvement over previous reference attacks, achieving on average two orders of magnitude runtime improvement. We also developed Fun-SAT+, which shifts the goal from finding the key to recovering the initial state of the circuit, and is agnostic of the key length. Our notion of functional corruptibility for sequential circuits and its monotonicity properties are independent of the specific locking scheme, making Fun-SAT and Fun-SAT+ effective methods for evaluating the security of various sequential logic locking schemes.
I'd like to thank my Ph.D. advisor Prof. Pierluigi Nuzzo, and all my collaborators Prof. Peter Beerel, Yuke Zhang, Kaixin Yang, and Dr. Dake Chen, for their support in making this research possible.
#research
#hardware
#intellectualproperty
#phd
#usc
#ieee
#cad
#security
I am excited to announce that I have joined Synopsys as a Senior Software Engineer! I interned with the same team in the summer of 2021 and have been inspired by their innovative work and the company culture. As a new member of the team, I look forward to catching up with this vibe and contributing to developing novel EDA solutions for the semiconductor industry. Big thanks to Pranay Prakash, Mark Wilkerson, Prachi Shahi, and the whole team for their warm welcome and help with my smooth transition!
]]>I have passed my Ph.D. dissertation defense, a milestone event in my life! Many thanks to my advisor Prof. Pierluigi Nuzzo and my defense committee members, Prof. Peter Beerel and Prof. Chao Wang, for their constructive feedback on my research. Many thanks to all my collaborators! I couldn't have achieved this without your support!
"Doctor Who" is on stage now!
]]>I am excited to announce that I have accepted an offer from Intel Corporation as a Security Research Intern at the Client Computing Group (CCG). A huge thanks to my hiring manager Chirag Shah and soon-to-be colleagues Rosario J D'Souza, Amir Khatib Zadeh, and KK Yu who interviewed me and provided me with valuable feedback on my PhD research in hardware security & trust. Thanks to Lisa Munger and Paula Valverde who assisted me a lot in making the recruiting process so smooth. As always, I deeply appreciate my professors Pierluigi Nuzzo and Peter Beerel for all the support and guidance.
]]>Our Work-In-Progress (WIP) paper "Circumventing Machine Learning-Based Attacks to Logic Locking" has been accepted to be presented as a poster in Design Automation Conference (DAC) 2022. Great thanks to my co-authors Subhajit Dutta Chowdhury and Kaixin Yang, our advisor Prof. Pierluigi Nuzzo. More details about this paper/poster to come in the next few weeks!
]]>I feel elated to share the news that our paper “TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks” has been accepted as a full paper at the Design, Automation, and Test in Europe Conference (DATE 2022), one of the top conferences in the EDA field. I want to thank my co-author Yuke Zhang for her dedicated contribution in the collaboration and our advisors Pierluigi Nuzzo and Peter Beerel for their constant support and help along the way!
]]>Officially become a Ph.D. candidate!
]]>I feel excited to share the news that our paper “Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption” has been accepted for publication at IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2021. Great thanks to my co-author YUKE ZHANG, our advisors Prof. Pierluigi Nuzzo and Prof. Peter Beerel, and the help from our team members Kaixin Yang and Dake Chen. In this paper, we introduce Fun-SAT, a functional corruptibility-guided SAT-based attack that can significantly decrease the SAT solving and model checking time of a SAT-based attack on sequential encryption by efficiently estimating the minimum required number of circuit unrollings. Fun-SAT relies on a notion of functional corruptibility for encrypted sequential circuits and its relationship with the required number of circuit unrollings in a SAT-based attack.
]]>Today marks the first day of my summer internship at Synopsys Looking forward to this experience and working with people with great minds in the next 12 weeks! #summerinternship2021
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