About me

profile_photo

I am a Staff Machine Learning Engineer at Altera, working at the intersection of machine learning, EDA systems, and hardware platforms. My focus is on building and scaling production-ready AI capabilities for FPGA products, with an emphasis on improving performance, productivity, and robustness across real-world silicon design workflows.

Previously at Synopsys, I worked on AI-driven design workflows across multiple stages, applying machine learning to improve optimization and decision-making across diverse design tasks. Building on this foundation, I later focused on prototyping next-generation agentic infrastructure for large-scale design systems, providing orchestration to coordinate execution across tools and agents and enabling end-to-end workflow automation in production environments.

I earned my Ph.D. in Electrical Engineering from the University of Southern California (USC). I also contribute to the technical community through reviewing and technical service for leading venues in design automation and hardware systems. You may find a list of my publications here.

Recent posts

LBR Paper accepted at DAC 2024

I'm excited to announce that our Late Breaking Results paper, "On the One-Key Premise of Logic Locking," has been accepted at DAC, The Chips to Systems Con...

Paper accepted at ISQED 2024

I'm thrilled to share that our research paper, "DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks," has been accepted for presentatio...

Paper accepted at IEEE TCAD

As hardware becomes more ubiquitous in our daily lives, protecting intellectual property (IP) and ensuring secure operations are paramount concerns. I'm ...

I passed my PhD defense at USC!!!

I have passed my Ph.D. dissertation defense, a milestone event in my life! Many thanks to my advisor Prof. Pierluigi Nuzzo and my defense committee membe...

WIP poster accepted at DAC 2022

Our Work-In-Progress (WIP) paper "Circumventing Machine Learning-Based Attacks to Logic Locking" has been accepted to be presented as a poster in Design ...

Paper accepted at DATE 2022

I feel elated to share the news that our paper “TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks” has been ac...