About me

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I am a staff machine learning engineer at Synopsys, a global leader in electronic design automation and semiconductor intellectual property (IP). I received my doctoral degree in Electrical Engineering at University of Southern California (USC) in 2022, advised by Prof. Pierluigi Nuzzo. Prior to my Ph.D. degree, I received my BSEE from Nankai University in 2017, and MSEE from USC in 2019.

At Synopsys, I conduct research on artificial intelligence (AI) and machine learning (ML) algorithms specifically for chip design. My work focuses on developing and integrating AI and ML algorithms into DSO.ai, the industry’s first autonomous AI application for chip design. This work complements my Ph.D. research interests, which focus on hardware security solutions for IP protection against threats on the integrated circuit (IC) supply chain, including the design and formal analysis of circuit obfuscation methods to prevent IC reverse-engineering. You may find a list of my publications here.

I currently serve on the Technical Program Committee for prestigious conferences, including the Design Automation Conference (DAC) and IEEE International Symposium on Hardware Oriented Security and Trust (HOST). In addition, I am also an External Reviewer for leading IEEE journals, specifically the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) and the IEEE Transactions on VLSI Systems (TVLSI).

Recent posts

Paper accepted at ISQED 2024

I'm thrilled to share that our research paper, "DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks," has been accepted for presentatio...

Paper accepted at IEEE TCAD

As hardware becomes more ubiquitous in our daily lives, protecting intellectual property (IP) and ensuring secure operations are paramount concerns. I'm ...

I passed my PhD defense at USC!!!

I have passed my Ph.D. dissertation defense, a milestone event in my life! Many thanks to my advisor Prof. Pierluigi Nuzzo and my defense committee membe...

WIP poster accepted at DAC 2022

Our Work-In-Progress (WIP) paper "Circumventing Machine Learning-Based Attacks to Logic Locking" has been accepted to be presented as a poster in Design ...

Paper accepted at DATE 2022

I feel elated to share the news that our paper “TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks” has been ac...

Paper accepted at HOST 2021

I feel excited to share the news that our paper “Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption” has been acce...

First day of internship at Synopsys

Today marks the first day of my summer internship at Synopsys Looking forward to this experience and working with people with great minds in the next 12 ...