Paper accepted at HOST 2021
I feel excited to share the news that our paper “Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption” has been acce...
I am a Staff Machine Learning Engineer at Altera, working at the intersection of machine learning, EDA systems, and hardware platforms. My focus is on building and scaling production-ready AI capabilities for FPGA products, with an emphasis on improving performance, productivity, and robustness across real-world silicon design workflows.
Previously at Synopsys, I worked on AI-driven design workflows across multiple stages, applying machine learning to improve optimization and decision-making across diverse design tasks. Building on this foundation, I later focused on prototyping next-generation agentic infrastructure for large-scale design systems, providing orchestration to coordinate execution across tools and agents and enabling end-to-end workflow automation in production environments.
I earned my Ph.D. in Electrical Engineering from the University of Southern California (USC). I also contribute to the technical community through reviewing and technical service for leading venues in design automation and hardware systems. You may find a list of my publications here.
I feel excited to share the news that our paper “Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption” has been acce...
Today marks the first day of my summer internship at Synopsys Looking forward to this experience and working with people with great minds in the next 12 ...
I was a Teaching Assistant for the course "VLSI System Design" (EE 577a) in Spring 2020. Today, I am glad to receive the Honorable Mention of the Charles...
I feel excited to share the news that I have been selected as a Young Fellow at the Design Automation Conference (DAC) 2020. DAC is recognized as the pre...