Publication
Doctoral Thesis:
Security-Driven Design of Logic Locking Schemes: Metrics, Attacks, and Defenses
Y. Hu, University of Southern California, Los Angeles, CA, USA, Dec. 2022.
Committee: Pierluigi Nuzzo (chair), Peter A. Beerel, and Chao Wang.
Book Chapters:
[b1] SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption
Y. Hu, K. Yang, S. Nazarian, P. Nuzzo, VLSI-SoC: Design Trends, Springer, 2021.
Journal Papers:
[j1] On the Security of Sequential Logic Locking Against Oracle-Guided Attacks
Y. Hu, Y. Zhang, K. Yang, D. Chen, P. A. Beerel, P. Nuzzo, IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), 2023.
Conference Papers:
[c12] Late Breaking Results: On the One-Key Premise of Logic Locking
Y. Hu, H. Cherupalli, M. Borza, D. Sherlekar, Design Automation Conference (DAC), June 2024.
[c11] DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
Y. Hu, K. Yang, S. Dutta Chowdhury, P. Nuzzo, International Symposium on Quality Electronic Design (ISQED), Apr. 2024.
[c10] Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
D. Chen, X. Zhou, Y. Hu, Y. Zhang, K. Yang, A. Rittenbach, P. Nuzzo, P. A. Beerel, International Symposium on Quality Electronic Design (ISQED), Apr. 2023.
[c9] TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks
Y. Zhang*, Y. Hu*, P. Nuzzo, P. A. Beerel, IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2022. [code]
[c8] Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption
Y. Hu*, Y. Zhang*, K. Yang, D. Chen, P. A. Beerel, P. Nuzzo, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Dec. 2021. [code]
[c7] Enhancing SAT-Attack Resiliency and Cost-Effectiveness of Reconfigurable-Logic-Based Circuit Obfuscation
S. Dutta Chowdhury, G. Zhang, Y. Hu, P. Nuzzo, IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
[c6] Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking
Y. Hu, K. Yang, S. Dutta Chowdhury, P. Nuzzo, IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Feb. 2021.
[c5] SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme
Y. Hu, K. Yang, S. Nazarian, P. Nuzzo, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2020.
[c4] Logic Obfuscation: Modeling Attack Resiliency
V. Menon, G. Kolhe, J. Fifty, A. G. Schmidt, J. Monson, M. French, Y. Hu, P. Beerel, and P. Nuzzo, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), Mar. 2020.
[c3] Security-driven Metrics and Models for Efficient Evaluation of Logic Encryption Schemes
Y. Hu, V. Venugopalan, A. Schmidt, J. Monson, M. French, P. Nuzzo, ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), Oct. 2019.
[c2] System-Level Framework for Logic Obfuscation with Quantified Metrics for Evaluation
V. Venugopalan, G. Kolhe, A. Schmidt, J. Monson, M. French, Y. Hu, P. A. Beerel, P. Nuzzo, IEEE Secure Development Conference (SecDev), Sept. 2019.
[c1] Quantifying Security and Overheads for Obfuscation of Integrated Circuits
V. Venugopalan, G. Kolhe, A. Schmidt, J. Monson, M. French, Y. Hu, P. A. Beerel, P. Nuzzo, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), Mar. 2019.
Demos & Posters:
[p3] Security-Driven Design of Logic Locking Schemes: Metrics, Attacks, and Defenses
Y. Hu, Design Automation Conference (DAC), July 2023. (Ph.D. Forum Presentation)
[p2] Circumventing Machine Learning-Based Attacks to Logic Locking
Y. Hu, S. Dutta Chowdhury, K. Yang, M. Munir, J. Bollareddy, P. Nuzzo, Design Automation Conference (DAC), July 2022.
[d1] MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
V. Venugopalan, G. Kolhe, A. Schmidt, J. Monson, M. French, Y. Hu, P. A. Beerel, P. Nuzzo, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2019.