Paper accepted at IEEE TCAD

As hardware becomes more ubiquitous in our daily lives, protecting intellectual property (IP) and ensuring secure operations are paramount concerns. I'm thrilled to announce that our research on hardware security has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems! Our work focuses on the security of Sequential Logic Locking, a class of IP protection methods. In our paper, we present Fun-SAT, a functional corruptibility-guided SAT-based attack that can efficiently estimate the minimum unrolling depth required for a successful SAT attack to prune out of the search space all the wrong keys. This is a major improvement over previous reference attacks, achieving on average two orders of magnitude runtime improvement. We also developed Fun-SAT+, which shifts the goal from finding the key to recovering the initial state of the circuit, and is agnostic of the key length. Our notion of functional corruptibility for sequential circuits and its monotonicity properties are independent of the specific locking scheme, making Fun-SAT and Fun-SAT+ effective methods for evaluating the security of various sequential logic locking schemes.

I'd like to thank my Ph.D. advisor Prof. Pierluigi Nuzzo, and all my collaborators Prof. Peter Beerel, Yuke Zhang, Kaixin Yang, and Dr. Dake Chen, for their support in making this research possible. #research #hardware #intellectualproperty #phd #usc #ieee #cad #security